VLSI

IEEE SSCS Delhi Chapter organized a workshop on VLSI Architectures for Communications and Signal Processing on 19th December, 2013 at ST Microelectronics, Greater Noida. The workshop was co-sponsored by Freescale, Agilent Technologies, Synopsys and India’s Premier Institute of Engineering, IIT Delhi.

Dronacharya Group of Institution, Greater Noida IEEE student members Rajan Sinha, Krishan Dev Mishra and Suyash Gupta of B.Tech, Information Technology attended the workshop along with Ms. Sarika Gupta, Department of Information Technology, Assistant Professor, Dronacharya Group of Institutions, Greater Noida.

The event started with the motivational words of Honorable Mr. Rakesh Malik, President, IEEE-SSCS. In his welcome speech he said that the workshop in Greater Noida aims to facilitate focused interactions between the distinguished IEEE lecturers and students while providing them with an opportunity to have a hands - on experience.

Dr. Kirann Gunnam, Director of Engineering, Violin Memory delivered an engaging lecture on VLSI architectures for Communications and Signal Processing Systems. Topics such as Pipelining and Parallel Processing, Retiming, Unfolding, Folding, Systolic Architecture Design and Algorithmic Transformations. The emphasis of the speaker was on how to design High-Speed, Low-area and Low-power VLSI systems for a broad range of DSP and Communication Applications.

The second half of his lecture covered his research findings. Low-Density Parity-Check codes Communication and Storage Channels, Turbo Equalization, System Level Hardware Architecture, Statistical Buffer Management and Queuing, Local-Global Inter-Leaver, LDPC Decoder and Error Floor Mitigation Schemes.

The session concluded with Dr. Malik saying that IEEE is pleased to sponsor VLSI Architecture perspectives for global outreach efforts. He expressed his sincere thanks to the organizers and to ST Microelectronics for hosting this event.