VLSI MARCH 2014

A one week Information and Communication Technology (ICT) based Short Training Program (STP) on ‘VLSI’ was organized at Dronacharya Group of Institutions, Greater Noida in association with NITTTR, Chandigarh during 10th - 14th March, 2014.

The session was started with a welcome speech from STP Coordinator Prof. Rajesh Mehra, Associate Professor, Electronics & Communication Engineering Department, NITTTR Chandigarh. Dr. M. P. Poonia, Director, NITTTR, Dr. S. B. L. Sachan, Head of Electronics & Communication Engineering and Dr. Balwinder Raj, VLSI Design Lab, Department of ECE were the dignitaries on the dice. Prof. (Dr.) M S Murali, Director, Dronacharya Group of Institutions, Greater Noida was the Chief Guest at DGI, GN network Center.In his welcome note he thanked to NITTTR, Chandigarh for conducting the workshop and requested Prof. Dr. M. P. Poonia Director NITTTR, Chandigarh to visit DGI, Greater Noida Campus.

Day First

The first session was on the topic ‘VLSI overview’ by Er. H. S. Jatana, Head-VLSI Design Division, Semiconductor Laboratory, Department of Space Mohali. Post lunch session was taken by Prof. Rajesh Mehra on the topic ‘VLSI Design Flow’. He covered the code development, simulation and synthesis, placement and routing (PAR) and implementation of VLSI using FPGA, SPLD, CPLD and ASIC.

Day Second

The first session was on the topic ‘VLSI Design Styles & Strategies’ and ‘Design Synthesis’ by Prof. Rajesh Mehra. A comparative study on PLDs, ASICs and FPGA and their pros and cons were shared by the speaker. He also discussed the architecture of all these three devices.

Second session of the day was taken by Dr. Balwinder Raj, VLSI Design Lab, Department of ECE, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar (NIT Jalandhar). He started the session with the introduction of VHDL and its programming.

Day Three

The agenda of the third day was on MOS Characteristics, CMOS design and device simulation. The speakers were Er. Arvind Rajput, Head- Electronics & Communication Department, UIET Chandigarh and Er. Amit. Saini, Cadre Design Systems, New Delhi. Mr. Arvind discussed the CMOS and MOS in depth and concluded that CMOS inverter is the foundation circuit of all other CMOS circuits. Mr. Amit, gives an overview on ‘Visual TCAD Semiconductor Device Simulator’.

Day Four

On the fourth day the main discussion was on ‘Recent VLSI Trends’ and ‘VLSI Challenges’ by Er. H. S. Jatana and ‘Embedded Design’ and ‘Embedded Application’ by Dr. J. S. Shambhi, Head- Electrical Engineering. Department, IIT Ropar Punjab. Er. H. S. Jatana gave the recent changes in the VLSI market from high performance to super high performance devices. He discussed the semiconductor market segments and distribution of these products in the market. He also shared a relative comparison of application and design tradeoffs. Dr. J. S. Shambhi discussed embedded system and VLSI role in embedded system.

Day Five

On the last day of the STP Dr. R. K. Sarin, Professor and Dean, NIT, Jalandhar, Punjab discussed ‘IC Fabrication’. He started from Moore’s Law and its prediction and Koomey’s Law. He gave an indepth knowledge on IC fabrication.

Valedictory session started with thanks giving by Prof. Rajesh Mehra, Dr. M. P. Poonia was the Chairperson. Prof. Rajesh asked the center to provide feedback from the participants. Prof. Vinod Kumar, Head- ECE Department, DGI, Greater Noida gave feedback about the STP on VLSI. He thanked NITTTR for conducting the STP on VLSI.