WORKSHOP - 10TH JAN'14

IEEE Solid State Circuit Society (SSCS) Delhi Chapter organized a workshop on Meeting the Signal Integrity Challenges of High-Speed Interconnecs and Systems in High speed links and System On Chip (SoC) at ST Microelectronics, Greater Noida on 10th January, 2014.

The workshop was co-sponsored by Freescale, Agilent Technologies, Synopsys, and India’s premier Institute of Engineering, IIT Delhi. One Faculty member Sarika Gupta and three students Rishikesh Kumar, Shivangi Pokhriyal and Ritika Tripathi IEEE members from Dronacharya Group of Institutions, Greater Noida. attended the workshop.

The event started with the motivational words of honorable Mr. Rakesh Malik, President of IEEE-SSCS. In his welcome speech he said that in today’s complex SoC designs, signal integrity considerations are very crucial due to multiprocessors and integrated high speed links (HDMI, DDR, MIPI etc.) getting integrated in miniaturized packages. His lecture focused on high speed aspects of complete system including multi-die packages and boards operating in high frequency domains. The talk was targeted for HSLINK designers, SoC designers/integrators, High speed Package/Board designers and validation engineers.

Prof. Ram Achar, Department of Electronics, Carleton University, Ottawa, Ontario delivered a lecture on Meeting the Signal Integrity Challenges of High-Speed Interconnects and Systems in High speed links and System On Chip (SoC). Prof. Achar is an active researcher contributing to the advancement of computer-aided design tools and methodologies for analysis of high-frequency circuits and systems.

During half of the technical session the System Level and Co-performance issues of signal integrity was discussed. Advanced signal integrity modeling/simulation strategies applicable to various levels of system hierarchy was described. The emphasis was placed on coupled interconnects. High-frequency current distribution related effects, such as skin, proximity were also focused upon.

The second half of his lecture emphasized on increasing demands of high signal speeds coupled with decreasing feature sizes and interconnect effects.

The session came to an end with a Vote of Thanks by Dr. Rakesh Malik. He thanked the Chief Guest, Prof. Ram Acharand allorganizers of ST Microelectronics for hosting this event.