DIGITAL SYSTEM DESIGN - DIGITAL ELECTRONICS

QEEE Session on “Digital System Design - Digital Electronics” was organized by IIT, Madras under D2S (Direct to Student) Program at Dronacharya Group of Institutions, Greater Noida on 6th, 13th and 17th February 2017. The session was conducted by Prof. T. G. Venkatesh (Assistant Professor, EE, IIT Madras). Mr. Raj Ranjan Prasad (Assistant Professor, ECE, DGI, Greater Noida) was the Local Faculty Coordinator for this session which was attended by students of ECE 4th Semester.

Day 1: 6th February 2017

Prof. T. G. Venkatesh began the first session with a lecture on basics of Digital Electronics i.e. Gates, Flip - Flops, Registers and Counters. He defined the sequential circuit and explained different types of Flip - Flops. He further discussed about Registers: Parallel load register, Shift Register, Universal shift register, Counters: Binary Ripple counter (up and down counter), Synchronous counters (up and down counter), 4-bit Synchronous up-down counter, Analysis of clocked sequential circuits, Counter design using state table (up counter), Counter design using D-flip flop, Counter design using JK-flip flop, Counter with unused states, Ring Counter and also design some digital circuits as well as cleared doubts of the students. The session ended with the Q & A session.

Day 2: 13th February 2017

Prof. T. G. Venkatesh initiated the second session with the lecture on Finite State Machine (FSM). He discussed the two types of FSM’s, Mealy (output is function of state and inputs) and Moore (output is only function of state). He further explained, Design of a Sequence Detector through Mealy machine and Moore machine. State table reduction using row reduction and using an Implication Table, Equivalent sequential circuits were also covered during the session. At the end of this lecture he answered questions asked by the students.

Day 3: 17th February 2017

The third and last session of this QEEE Program started with Prof. Venkatesh’s lecture on Memory Devices. He explained about state table, read cycle and write cycle. He then gave a description of combinational circuits, in which he explained Dataflow. He explained Process Block in VHDL models for sequential circuits topic. He also explained about ASM (Algorithmic State Machine) charts and Components of ASM charts; FSM / ASM chart Realization by One hot method, using multiplexers, using ROM, State Table Reduction using an Implication Table. The program came to an end at 12:10 PM.

The QEEE session was very beneficial for the students and will add in-depth knowledge and help them to solve conceptual questions related to the topic.

Glimpses of the Session: