WORKSHOP-VERILOG

A workshop on Verilog was organized by NcrEdu Services Private Limited, Indirapuram, Ghaziabad on 12th, 13th and 14th December, 2013. Mr. Sapan Kumar Gupta and Mr. Shiv Bhushan, Assistant Professor, ECE Department of Dronacharya Group of Institutions, Greater Noida attended the workshop. The trainers of the workshop were fromi.e. Zabil Technologies Pvt. Ltd. and Cadence Design systems.

Workshop started on 12th December, 2013 with the course description and significance of Verilog in digital hardware design. After a brief history of Verilog and evolution of hardware description languages were discussed. The modules discussed on the first day were Course Introduction, Hardware Modeling Overview, Language introduction, Data Types and logic system, Modeling Structures, Operators, Procedural statements, Continuous and Procedural Statements, Procedural Statements and the Simulation Cycle. The workshop was discussion oriented with practical approach and all the modules of the workshop were discussed in detail followed by some practical simulations. It enhanced the learning of digital design with basic and advanced coding techniques for Verilog Synthesis. The main modules of the workshop were: Verilog, Sample Design, Verification Constructs, Coding Design Behavior Algorithmically, Finite State Machines etc.

On 13th December, 2013 Procedural Statements, Blocking and Non-Blocking Assignments and Functions were primarily discussed but ‘Testbenches’ was the tag title of the day.

On 14th December, 2013 most significant aspect of the workshop – “RTL Verification” was discussed thoroughly. Apart from it Verification Constructs, Compiler Directives and Designing of Finite State Machine were also in the lime light.